Staff Design Verification Engineer

Our client is seeking an experienced Staff Design Verification Engineer to join a dynamic team focused on developing ultra-low power semiconductor solutions for AI edge designs in Internet of Things (IoT) applications. The ideal candidate will have 8-12 years of experience in semiconductor design verification and a proven track record of success in developing and executing verification plans for complex SoC designs.

Responsibilities

• Verify digital and mixed-signal designs, including systems-on-chip with multiple CPUs, digital signal processors, and security hardware for IoT applications.
• Develop test plans at block, sub-system, and chip levels.
• Execute SoC-based verification at full-chip.
• Write C-based library packages and tests.
• Architect and implement scalable and reusable test benches using SystemVerilog and UVM.
• Develop comprehensive test cases, stimulus generation, and checkers to achieve high coverage.
• Automate the test environment for randomized testing and scoreboarding.
• Utilize advanced debugging techniques to identify and resolve design and verification issues.
• Perform root-cause analysis and collaborate with design teams to address identified issues.
• Define and track functional and code coverage metrics to ensure thorough verification.
• Ensure that verification quality meets or exceeds industry standards and project requirements.
• Edge-based AI inference experience is preferred.

• BSEE/MSEE degree with 5-8 years of experience in block, sub-system, and full-chip verification.
• Experience delivering multiple chips functioning to specification.
• Proven ability to identify and manage verification deliverables, milestones, and schedules.
• Strong understanding of multiple architectures, integrating 3rd party IPs/VIPs, and mixed-signal designs.
• Strong exposure to design verification for low-power battery-operated designs.
• Proficiency in C-based verification in an SoC environment.
• Experience with ARM processor-based designs and low-power design techniques is a plus.
• Languages: SystemVerilog (UVM), Verilog, C/C++, Python, Perl, or Makefile.
• Technologies: ARM M/RISC-V (preferred), AMBA AXI/AHB/APS, DMA, Flow Control, Serial Devices, Qo5.

• Strong experience in low-power implementation methodologies.
• Advanced timing signoff methodology experience.
• Knowledge of DFT (BSCAN, MBIST, SCAN) and its impact on physical design flows.
• Ability to independently complete Netlist-GDS P&R and signoff tasks.
• Proven record in multi-million gate design production tapeouts.
• Preferred technologies include MIPI (CSI/DSI), Crypto, OTP, DSP, and low-power solutions.